Branch Optimisation Techniques for Hardware Compilation

Optimisation of Hardware Compilation using Programmable Transformations

Compiling Policy Descriptions into Reconfigurable Firewall Processors

We describe a framework for capturing firewall requirements as high-level descriptions based on the policy specification language Ponder. The framework provides abstraction from hardware implementation while allowing performance control through constraints. Our hardware compilation strategy for such descriptions involves a rule reduction step to produce a hardware firewall rule representation. ...

Area Optimisation in SystemC Hardware Compilation

Hardware compilation translates a program written in a high-level language into a description of a hardware circuit. Hardware compilation shortens development time compared to traditional hardware design. However, currently it often produces less efficient hardware, measured in speed and logic area. This report describes three methods to improve logic area of a design. The first method is resou...

Provably Correct Hardware Compilation using Timing Diagrams

In this article we present a framework within which hardware implementations are proven correct from speciications given in an OCCAM-like language called Handel by the use of a robust set of mathematical trans-formational laws. The semantical basis for Handel and its hardware implementations are simple functions of time which are called timing diagrams. This basis allows to denote the abstract ...

Research Proposal : Michael O ’ Boyle

This project aims to develop a new framework which enables compilers to adapt with and exploit the exponential growth in hardware performance. This is achieved by systematically describing the program optimisation space and by developing new approaches to explore this space in a manner independent of application or underlying architecture. Furthermore, by transcending the distinction between co...